Interphase Tech CONDOR 4221 Bedienungsanleitung

V/Ethernet 4221 Condor User’s GuideDocument No. UG04221-000, REVBRelease date: July 1994Copyright 1994Interphase CorporationAll Rights Reserved

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Chapter 3 - MACSI Host Interface88Command Options Table 3-30. Command OptionsInterrupt enable (IE) As defined in Common IOPB Structures. In-line gathe

Transmit -- In-Line Gathers89Table 3-31. Transmit - In-Line GathersNumber of Elements This field contains the number of gather elements included in th

Chapter 3 - MACSI Host Interface90Receive The host provides the controller with Receive commands, which specify the host resources to be used for inco

Receive91Command Code This field must contain 0x60 to execute the Receive IOPB. Command Options Table 3-33. Command OptionsInterrupt enable As defined

Chapter 3 - MACSI Host Interface92Source Address When so monitoring the network, the source address for the incoming frame will be contained in this f

Initialize Multiple Completions93Initialize Multiple Completions This command enables the controller to return multiple completed commands to the host

Chapter 3 - MACSI Host Interface94Command Options No special options are available for this command. Refer to Common IOPB structures for defined opti

Report Network Statistics95Report Network Statistics Table 3-36. Report Network StatisticsThe Report Network Statistics Command can be used to obtain

Chapter 3 - MACSI Host Interface96Command Options Table 3-37. Command OptionsInterrupt enable (IE) As defined in Common IOPB Structures. Port selector

Network Statistics Block97Network Statistics Block Table 3-38. Network Statistics BlockData Valid Indicator When the data is transferred to the host,

LIST OF TABLESxivTable 2-1. Condor Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 3 - MACSI Host Interface98Transmits Failed This field contains the number of transmit commands for the particular port that could not be trans

99APPENDIX A SPECIFICATIONSVMEbus SpecificationsDTB Master A16, A24, A32, D08 (EO), D16, D32: BLT, D64: BLTDTB Slave A16, D08 (EO), D16, D32Request

100Appendix AMechanical (Nominal)Length 233 mmWidth 160 mmThickness 20 mmWeight .45 KgOperating EnvironmentTemperature 0-55 degrees CentigradeRelative

101APPENDIX B CONNECTOR PINOUTS AND CABLINGOverviewThis chapter contains the connector pinouts and cabling information needed for various Condor confi

102Appendix BVMEbus ConnectorsThe following tables show the pin numbers and signal description for the P1 and P2 VMEbus Connectors.• Table C-39 - P1 C

103VMEbus ConnectorsP2 Connector Row B Only VersionTable C-40. P2 Connector For Motherboards Which Only Uses P2 Row BPINRow A Signal Mnemonic Row B Si

104Appendix BEthernet Connectors and PinoutsThe Condor supports both the AUI and 10BaseT versions of the Ethernet 802.3 specification. The card will h

105Ethernet Connectors and PinoutsAUI Connector SignalsThe AUI signals and connector pinout for the DB15 connector are shown in the following table.Ta

106Appendix BRS232 Connector and CableTable C-43. Serial Connector Pinouts (SPA and SPB)NOTE: The same cable for the second Serial Port for PC compa

107APPENDIX C ERROR CODESThe Return Status word in the command response contains information pertaining to the status of the IOPBs returnedin the Comm

xvTable 3-36. Report Network Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Tab

108Appendix B

INDEX109Numerics82596 4, 81, 82AAA 79Abort ALL (AA) 79Abort ANY (AN) 79Abort Pending (AP) 81Abort Report (AR) 80, 81Air Flow 100AN 79ANY 91AP 81AR

110EX 63Exception (EX) 63Ffeature list 2fetch offboard entry (FOB) 60Fetch offboard in progress (FIP) 60field offset 54FIP 60firmware revision level 6

111PPFM 86PM 75, 81POST mode 15power requirements 99Product Code 65, 68Program factory MAC address (PFM) 86Promiscuous mode (PM) 75, 81QQECR 60QMS

112

1CHAPTER 1 INTRODUCTIONIntended AudienceInterphase wrote this manual for its customers. It is intended for a highly technical audience, specifically,

Chapter 1 - Introduction2ConventionsThis section details many of the writing conventions used throughout the manual. In addition, it gives many of th

Options3OptionsInterphase Corporation offers the following Condor options:• Dual Channel Ethernet (AUI)• Dual Channel Ethernet (10BaseT)• 3 Channel Et

Chapter 1 - Introduction4Ethernet Front End Channel (FEC)The 82596CA® Local Area Network (LAN) Co-processor is used as the FEC Ethernet controller. Th

VMEbus Short I/O Interface5VMEbus Short I/O InterfaceThe VMEbus Short I/O interface allows for VMEbus host and onboard CPU communications. The host is

Chapter 1 - Introduction6interrupt handler outputs an interrupt vector number for the non-DMA engine interrupts or requests access to the LBUSfor a DM

7CHAPTER 2HARDWARE INSTALLATIONOverviewBefore attempting installation, read this chapter thoroughly to insure the safe installation of the Condor int

Chapter 2 - Hardware Installation8The daughter card installation procedure will vary depending on the desired configuration. Variables include:• Sing

Overview9Figure 2-1. 10BaseT Condor Motherboard Layout (PB04221-000)LED 1LED 2LED 3LED 4LED 5LED 6LED 7SPBSPAJ14J15J16J18J12J13P2P1J23J24J26J25J19J2

Chapter 2 - Hardware Installation10Figure 2-2. Single Channel AUI or 10BaseT Motherboard Layout (PB004221-001)LED 1LED 2LED 3LED 4LED 5LED 6SPBSPAJ1

Overview11Figure 2-3. AUI Condor Motherboard Layout (PB04221-000)LED 1LED 2LED 3LED 4LED 5LED 6SPBSPAJ14J15J16J18J12J13P2P1J23J24J26J25J19J20J21J22

Chapter 2 - Hardware Installation12Figure 2-4. 10BaseT Condor Motherboard Layout (PB04221-001)LED 1LED 2LED 3LED 4LED 5LED 6LED 7SPBSPAJ10 J14 J16J1

Overview13Figure 2-5. AUI Condor Motherboard Layout (PB04221-001)LED 1LED 2LED 3LED 4LED 5LED 6SPBSPAJ10 J14J16J18J12J15P2P1J23J24J26J25J19J20J21J2

Chapter 2 - Hardware Installation144221 Condor Hardware Installation ProceduresFor proper installation of the Condor, it is imperative that you use th

4221 Condor Hardware Installation Procedures15Board Status LEDsLEDs 1, 2, 3, and 4 are Board Status LEDs which provide the following functions:• Power

Chapter 2 - Hardware Installation16Table 2-4. Run Mode LED MatrixStep 3. Set Onboard Motherboard Jumpers Set all onboard jumpers so that the Condor i

4221 Condor Hardware Installation Procedures17J9 +12 VOLTS Flash Programming Protect: IN: +12 Volt power connected to EPROM socket.OUT: +12 Volt power

Copyright Notice Copyright 1993, 1994 by Interphase CorporationAll rights reservedNo part of this publication may be stored in a retrieval system, tr

Chapter 2 - Hardware Installation18(Pins 5-6) Console Message DisableIN = DisableOUT = Enable(Pins 7-8) GDB Enable PointIN = GDB Initialized On ExitOU

4221 Condor Hardware Installation Procedures19Table 2-6. Secondary Short I/O* Factory DefaultJ16 Primary Short I/O Size / Reset Enable:Table 2-7. Prim

Chapter 2 - Hardware Installation20J18 Primary Channel Address Modifiers:IN = Primary Channel Address Modifiers 29 or 2D OUT = Primary Channel Addres

4221 Condor Hardware Installation Procedures21J19, J20, J21 & J22 Primary Short I/O Base Address:Refer to the following tables when setting Primar

Chapter 2 - Hardware Installation22Table 2-8. Primary Base Address For 2K Short I/O NOTE: 0 = IN (Logical 0), F = OUT (Logical 1)ADDRESS J19 PIN SETTI

4221 Condor Hardware Installation Procedures23Table 2-9. Primary Base Address For 1K Short I/O NOTE: 0 = IN (Logical 0), F = OUT (Logical 1)ADDRESS J1

Chapter 2 - Hardware Installation24Table 2-10. Primary Base Address For 512 Byte Short I/ONOTE: 0 = IN (Logical 0), F = OUT (Logical 1)ADDRESS J19 PIN

4221 Condor Hardware Installation Procedures25Table 2-10. Primary Base Address For 512 Byte Short I/O (Continued)NOTE: 0 = IN (Logical 0), F = OUT (Lo

Chapter 2 - Hardware Installation26Table 2-11. Primary Base Address For 256 Byte Short I/O NOTE: 0 = IN (Logical 0), F = OUT (Logical 1)ADDRESS J19 PI

4221 Condor Hardware Installation Procedures27Table 2-11. Primary Base Address For 256 Byte Short I/O (Continued)NOTE: 0 = IN (Logical 0), F = OUT (Lo

For AssistanceTo place an order for an Interphase product, call:Sales Support: (214) 919-9000For assistance using this, or any other Interphase produ

Chapter 2 - Hardware Installation28Table 2-11. Primary Base Address For 256 Byte Short I/O (Continued)NOTE: 0 = IN (Logical 0), F = OUT (Logical 1)ADD

4221 Condor Hardware Installation Procedures29Table 2-11. Primary Base Address For 256 Byte Short I/O (Continued)NOTE: 0 = IN (Logical 0), F = OUT (Lo

Chapter 2 - Hardware Installation30Table 2-11. Primary Base Address For 256 Byte Short I/O (Continued)NOTE: 0 = IN (Logical 0), F = OUT (Logical 1)ADD

4221 Condor Hardware Installation Procedures31Table 2-11. Primary Base Address For 256 Byte Short I/O (Continued)NOTE: 0 = IN (Logical 0), F = OUT (Lo

Chapter 2 - Hardware Installation32Table 2-11. Primary Base Address For 256 Byte Short I/O (Continued)NOTE: 0 = IN (Logical 0), F = OUT (Logical 1)ADD

4221 Condor Hardware Installation Procedures33J23, J24, J25 & J26 Secondary Short I/O Address:Refer to the following tables when setting Secondary

Chapter 2 - Hardware Installation34Table 2-12. Secondary Base Address For 2K Short I/ONOTE: 0 = IN (Logical 0), F = OUT (Logical 1)ADDRESS J23 PIN SET

4221 Condor Hardware Installation Procedures35Table 2-13. Secondary Base Address For 1K Short I/O NOTE: 0 = IN (Logical 0), F = OUT (Logical 1)ADDRESS

Chapter 2 - Hardware Installation36Table 2-13. Secondary Base Address For 1K Short I/O (Continued)NOTE: 0 = IN (Logical 0), F = OUT (Logical 1)ADDRESS

4221 Condor Hardware Installation Procedures37Table 2-14. Secondary Base Address For 512 Byte Short I/O NOTE: 0 = IN (Logical 0), F = OUT (Logical 1)A

TABLE OF CONTENTSviCHAPTER 1INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 2 - Hardware Installation38Table 2-14. Secondary Base Address For 512 Byte Short I/O (Continued)NOTE: 0 = IN (Logical 0), F = OUT (Logical 1)A

4221 Condor Hardware Installation Procedures39Table 2-14. Secondary Base Address For 512 Byte Short I/O (Continued)NOTE: 0 = IN (Logical 0), F= OUT (L

Chapter 2 - Hardware Installation40Table 2-14. Secondary Base Address For 512 Byte Short I/O (ContinuedADDRESS J23 PIN SETTINGS J24, J25, J26 PIN SETT

4221 Condor Hardware Installation Procedures41Table 2-15. Secondary Base Address For 256 Byte Short I/O NOTE: 0 = IN (Logical 0), F = OUT (Logical 1)A

Chapter 2 - Hardware Installation42Table 2-15. Secondary Base Address For 256 Byte Short I/O (Continued)NOTE: 0 = IN (Logical 0), F = OUT (Logical 1)A

4221 Condor Hardware Installation Procedures43Table 2-15. Secondary Base Address For 256 Byte Short I/O (Continued)NOTE: 0 = IN (Logical 0), F= OUT (L

Chapter 2 - Hardware Installation44Table 2-15. Secondary Base Address For 256 Byte Short I/O (Continued)NOTE: 0 = IN (Logical 0), F = OUT (Logical 1)A

4221 Condor Hardware Installation Procedures45Table 2-15. Secondary Base Address For 256 Byte Short I/O (Continued)NOTE: 0 = IN (Logical 0), F = OUT (

Chapter 2 - Hardware Installation46Table 2-15. Secondary Base Address For 256 Byte Short I/O (Continued)NOTE: 0 = IN (Logical 0), F = OUT (Logical 1)A

4221 Condor Hardware Installation Procedures47Step 4. Set Daughter Card Jumpers And TerminationsThe following daughter card settings are discussed:• E

viiCommand Response Block (CRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 2 - Hardware Installation48Ethernet Single Channel AUI/10BaseT Daughter CardCOMPONENT SIDE Figure 2-6. Ethernet Single Channel AUI/10Ba

4221 Condor Hardware Installation Procedures49Dual Channel 10BaseT Ethernet Daughter CardCOMPONENT SIDE Figure 2-7. Dual Channel 10BaseT Ethernet Da

Chapter 2 - Hardware Installation50Ethernet Dual Channel AUI Daughter CardCOMPONENT SIDE Figure 2-8. Ethernet Dual Channel AUI Daughter CardNOTE: L

4221 Condor Hardware Installation Procedures51Step 5. Power Off SystemOnce the board is configured, ensure that the host system and peripherals are tu

Chapter 2 - Hardware Installation52RS232 Connectors And CablesThere are two 10 pin connectors (2x5 Headers) which are used as the RS232 port cable con

53CHAPTER 3MACSI HOST INTERFACEIntroductionThis chapter defines the MACSI host interface for the Interphase V/Ethernet 4221 Condor. The Condor and it

Chapter 3 - MACSI Host Interface54Field OffsetThe value in the far left column specifies the field offset. This value measures increments of 16 bits

System Interface55System Interface This section defines how the host communicates with the controller. The shared memory interface is defined, and ea

Chapter 3 - MACSI Host Interface56The Master Command Entry (MCE) and Command Queue Entries (CQE) are used to queue commands from the hostto the contr

Master Control Status Block (MCSB)57Master Control Status Block (MCSB)The MCSB consists of a Master Status Register, which is used to report informati

viiiMAC status/control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 3 - MACSI Host Interface58Master Control Register (MCR)The MCR provides the host with infrequently used services. These bits are both set and

Onboard Command Queue Entry59Onboard Command Queue Entry The host issues a command to the controller through a Command Queue Entry (CQE). Two types a

Chapter 3 - MACSI Host Interface60Fetch offboard (FOB) Setting this bit makes the Command Queue entry an offboard entry. Please see the following sect

Offboard Command Queue Entry61DMA Transfer Control Word This field specifies how the controller should DMA transfer the data from host memory. This f

Chapter 3 - MACSI Host Interface62Command Response Block (CRB)The CRB is used by the controller to post completed commands back to the host. It consi

Command Response Block (CRB)63Error (ER) This bit is set with Command Complete when a returned IOPB completed with an error. Errored commandsare nev

Chapter 3 - MACSI Host Interface64Multiple Completed Returned IOPB Structure When multiple commands are returned from the controller to the host with

Configuration Status Block (CSB)65Configuration Status Block (CSB)The controller uses the CSB to report the firmware and hardware configuration upon p

Chapter 3 - MACSI Host Interface66Firmware Revision Level The firmware revision level, represented as a 3-digit ASCII value. Firmware Revision Date Th

Controller Statistics Block67Controller Statistics Block This space was used to report network statistics in the original Eagle MACSI implementation f

ixOperating Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 3 - MACSI Host Interface68Transmit Commands Submitted Total number of attempted frame transmissions (successful and unsuccessful). Transmit DM

Controller Statistics Block69Transmit Completions Posted to Host Total number of frame completions posted to the Command Response Block and Returned I

Chapter 3 - MACSI Host Interface70IO Parameter Blocks (IOPBs) This section provides a detailed description of each of the commands used by the host to

Common IOPB Structures71Command Code This field specifies the command to be executed. Particular values are noted for each of the individual commands

Chapter 3 - MACSI Host Interface72Address modifier This field contains the VMEbus address modifier used for the transfer. Refer to your system documen

Initialize Controller73Initialize Controller This command allows the host to specify global configuration parameters, and initializes the controller f

Chapter 3 - MACSI Host Interface74Controller Initialization Block (CIB)The CIB contains the actual values to use when initializing the controller. It

Controller Initialization Block (CIB)75Special Network Options Originally, this field allowed the host to set several network related options, such as

Chapter 3 - MACSI Host Interface76A value between 1 and 0x20 (40 decimal) causes the controller, after being granted the bus, to transfer data until 1

MAC Control/Status77MAC Control/Status This command provides a host driver with two distinct levels of service to an Ethernet port located on the 4221

LIST OF FIGURESxiiFigure 1-1. 4221 Condor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 3 - MACSI Host Interface78Table 3-22. MAC Control / StatusCommand Code This field must contain 0x43 to execute the MAC Control IOPB. MAC Contr

MAC Control/Status79Command Options Table 3-23. Command OptionsInterrupt Enable (IE) Defined in Common IOPB Structures. Set MAC options (SM) When this

Chapter 3 - MACSI Host Interface80Abort Report (AR)Setting this bit causes commands aborted with either the AA or the AN bit to be reported back to th

MAC Control/Status81Setting this bit resets the port: promiscuous mode is disabled, multicast is disabled, any supplied multipleindividual addresses a

Chapter 3 - MACSI Host Interface82Table 3-25. Intel 82596 Transmit Status / ControlBackoff method (BM) (p. 4-131) This parameter determines when to st

MAC Control/Status83Table 3-26. Intel 82596 Receive Status / ControlSave bad frames (SB) (p. 4-129)When set bad frames (CRC error, Alignment error, et

Chapter 3 - MACSI Host Interface84Time domain reflectometry test (TDR) (p. 4-150) This operation activates the Time Domain Reflectometry test. The re

Change Default Node Address85Change Default Node Address This command is used to change the 48 bit physical address associated with any of the attache

Chapter 3 - MACSI Host Interface86Command Options Table 3-28. Command OptionsInterrupt enable (IE)As defined in the Common IOPB Structures. Update use

Transmit87Transmit The Transmit command causes the controller to DMA transfer the specified frame from host memory, and thentransmit it (if possible)